1. Field of the Invention
The present invention relates to a shift register, and more particularly to a shift register including a plurality of blocks of unit circuits for transferring data in one direction based on a clock signal having pulses.
2. Description of the Background Art
A conventional shift register will now be described. FIG. 16 shows a configuration of the conventional shift register.
Referring to FIG. 16, the shift register includes four blocks of unit circuits 1-1 to 1-4 and transfers data from left to right in FIG. 16 based on two clock signals CLK1 and CLK2 having a predetermined period. The clock signals CLK1 and CLK2 are signals having pulses that appear with the same period but in an alternating manner. A unit circuit 1 outputs an output signal NEXT (i.e., data being transferred) to another unit circuit 1 of an adjacent block downstream in the data transfer direction (hereinafter referred to as the “subsequent block”), and outputs an output signal OUT at the same time. The output signal OUT serves as a reset signal RS for erasing data stored in another unit circuit 1 of an adjacent block upstream in the data transfer direction (hereinafter referred to as the “preceding block”). The output signal NEXT serves as an input signal IN to the unit circuit 1 of the subsequent block. Referring to FIG. 17, the unit circuit 1 will now be described in greater detail. FIG. 17 is a circuit diagram showing a detailed configuration of the unit circuit 1.
First, the circuit configuration of the unit circuit 1 will be described. Referring to FIG. 17, the unit circuit 1 includes a transistor 3, a capacitor 5, a transistor 7 and a transistor 9. The drain of the transistor 3 is connected to the signal line of the clock signal CLK1, and the clock signal CLK1 is received via the drain of the transistor 3. The input signal IN is applied to the gate of the transistor 3. The source of the transistor 3 is connected to the drain of the transistor 7. The source of the transistor 3 is also connected to the unit circuit 1 of the preceding block, and the output signal OUT is outputted via the source of the transistor 3.
The gate of the transistor 7 is connected to the drain of the transistor 7. The source of the transistor 7 is connected to the unit circuit 1 of the subsequent block, and the output signal NEXT is outputted via the source of the transistor 7. The capacitor 5 is connected between the gate and the source of the transistor 3.
The input signal IN is applied to the drain of the transistor 9. The reset signal RS is applied to the gate of the transistor 9. The source of the transistor 9 is grounded.
The functions of the components of the unit circuit 1 shown in FIG. 17 will now be described. The transistor 3 selectively outputs or does not output the clock signal based on the voltage value of the input signal IN applied to the gate thereof. Specifically, the transistor 3 outputs the clock signal CLK via the source thereof if the input signal IN has a voltage at a high level indicating data of “1”. If the input signal IN has a voltage at a low level, the transistor 3 does not output the clock signal CLK via the source thereof. In such a case, the potential at the source of the transistor 3 is equal to the low level of the clock signal CLK.
The capacitor 5 serves to store data being transferred from the unit circuit 1 of the preceding block. The capacitor 5 may be a capacitor formed between the gate and the drain of the transistor 3 or a capacitor formed between the gate and the source of the transistor 3, or may be a separately-provided capacitor.
The transistor 7 is a switch that determines whether or not the clock signal CLK from the source of the transistor 3 is to be outputted as the output signal NEXT. Specifically, a voltage at the high level indicating data of “1” is outputted from the source of the transistor 7 as the output signal NEXT if a voltage at the high level is applied to the gate and the drain thereof. If a voltage at the low level is applied to the gate and the drain of the transistor 7, a voltage at the low level is outputted from the source thereof as the output signal NEXT.
The transistor 9 erases data stored in the capacitor 5 using the output signal OUT from the unit circuit 1 of the subsequent block as the reset signal RS. Thus, the transistor 9 serves to clear the data stored in the unit circuit 1 to which it belongs after the unit circuit 1 to which it belongs outputs the charge being transferred.
Referring to FIG. 18, the operation of the conventional shift register having such a configuration will now be described. FIG. 18 shows voltage transitions of various signals when the conventional shift register is transferring data.
At t=0, the unit circuit 1-1 receives data to be transferred. Specifically, the unit circuit 1-1 receives the input signal IN1 having a voltage at the high level. The data is stored in the capacitor 5 of the unit circuit 1-1, and the gate potential of the transistor 3 of the unit circuit 1-1 increases to the high level. As a result, the transistor 3 of the unit circuit 1-1 is turned ON.
At t=2, the voltage of the clock signal CLK1 transitions to the high level. Since the transistor 3 of the unit circuit 1-1 is ON, the transistor 3 outputs the clock signal CLK1 having a voltage at the high level via the source thereof. Thus, the voltage of the output signal OUT1 increases to the high level. Moreover, the gate potential of the transistor 3 of the unit circuit 1-1 (i.e., the voltage of the input signal IN1) increases.
Moreover, at t=2, a voltage at the high level is applied to the gate and the drain of the transistor 7 of the unit circuit 1-1. Thus, the transistor 7 of the unit circuit 1-1 is turned ON. As a result, the voltage of the output signal NEXT1 increases to the high level. Thus, data is transferred from the unit circuit 1-1 to the unit circuit 1-2.
At t=3, the voltage of the clock signal CLK1 decreases to the low level. Accordingly, the voltage of the output signal OUT1 also decreases to the low level. Similarly, the gate potential of the transistor 3 of the unit circuit 1-1 (i.e., the voltage of the input signal IN1) decreases.
Moreover, at t=3, as the voltage of the clock signal CLK1 decreases to the low level, the gate potential and the drain potential of the transistor 7 of the unit circuit 1-1 also decrease. As a result, the transistor 7 of the unit circuit 1-1 is turned OFF.
At t=4, the voltage of the clock signal CLK2 transitions to the high level. Since the transistor 3 of the unit circuit 1-2 is ON, the transistor 3 outputs the clock signal CLK2 having a voltage at the high level via the source thereof. Thus, the voltage of the output signal OUT2 increases to the high level. Moreover, the gate potential of the transistor 3 of the unit circuit 1-2 (i.e., the voltage of the input signal IN2) increases.
The output signal OUT2 is used as the reset signal RS1 for the unit circuit 1-1. Therefore, as the voltage of the output signal OUT2 increases, the voltage of the reset signal RS1 also increases, thus clearing data stored in the capacitor 5 of the unit circuit 1-1. As a result, the gate potential of the transistor 3 of the unit circuit 1-1 (i.e., the voltage of the input signal IN1) decreases to the low level.
Moreover, at t=4, the clock signal CLK2 at the high level is applied to the gate and the drain of the transistor 7 of the unit circuit 1-2. Thus, the transistor 7 of the unit circuit 1-2 is turned ON. As a result, the voltage of the output signal NEXT2 increases to the high level. Thus, data is transferred from the unit circuit 1-2 to the unit circuit 1-3.
At t=5, the voltage of the clock signal CLK2 decreases to the low level. Accordingly, the voltage of the output signal OUT2 also decreases to the low level. Similarly, the gate potential of the transistor 3 of the unit circuit 1-2 (i.e., the voltage of the input signal IN2) decreases.
Moreover, at t=5, as the voltage of the clock signal CLK2 decreases to the low level, the gate potential and the drain potential of the transistor 7 of the unit circuit 1-2 also decrease. As a result, the transistor 7 of the unit circuit 1-2 is turned OFF.
At t=6, the voltage of the clock signal CLK1 transitions to the high level. Since the transistor 3 of the unit circuit 1-3 is ON, the transistor 3 outputs the clock signal CLK1 having a voltage at the high level via the source thereof. Thus, the voltage of the output signal OUT3 increases to the high level. Moreover, the gate potential of the transistor 3 of the unit circuit 1-3 (i.e., the voltage of the input signal IN3) increases.
The output signal OUT3 is used as the reset signal RS2 for the unit circuit 1-2. Therefore, as the voltage of the output signal OUT3 increases, the voltage of the reset signal RS2 also increases, thus clearing data stored in the capacitor 5 of the unit circuit 1-2. As a result, the gate potential of the transistor 3 of the unit circuit 1-2 (i.e., the voltage of the input signal IN2) decreases to the low level.
Moreover, at t=6, the clock signal CLK1 at the high level is applied to the gate and the drain of the transistor 7 of the unit circuit 1-3. Thus, the transistor 7 of the unit circuit 1-3 is turned ON. As a result, the voltage of the output signal NEXT3 increases to the high level. Thus, data is transferred from the unit circuit 1-3 to the unit circuit 1-4.
At t=7, the voltage of the clock signal CLK1 decreases to the low level. Accordingly, the voltage of the output signal OUT3 also decreases to the low level. Similarly, the gate potential of the transistor 3 of the unit circuit 1-3 (i.e., the voltage of the input signal IN3) decreases.
Moreover, at t=7, as the voltage of the clock signal CLK1 decreases to the low level, the gate potential and the drain potential of the transistor 7 of the unit circuit 1-3 also decrease. As a result, the transistor 7 of the unit circuit 1-3 is turned OFF.
At t=8, the voltage of the clock signal CLK2 transitions to the high level. Since the transistor 3 of the unit circuit 1-4 is ON, the transistor 3 outputs the clock signal CLK2 having a voltage at the high level via the source thereof. Thus, the voltage of the output signal OUT4 increases to the high level. Moreover, the gate potential of the transistor 3 of the unit circuit 1-4 (i.e., the voltage of the input signal IN4) increases.
Moreover, at t=8, the clock signal CLK2 at the high level is applied to the gate and the drain of the transistor 7 of the unit circuit 1-4. Thus, the transistor 7 of the unit circuit 1-4 is turned ON. As a result, the voltage of the output signal NEXT3 increases to the high level. Thus, data is outputted from the unit circuit 1-4.
The conventional shift register shown in FIG. 16 transfers data from left to right through an operation as described above.
Various methods for transferring data by a shift register are known in the art, e.g., the method disclosed in Japanese Laid-Open Patent Publication No. 2001-273785.
The conventional shift register as described above has a problem in that a portion of the unit circuit 1-1 between the source of the transistor 3 and the gate of the transistor 7 (i.e., the portion via which the output signal OUT1 is outputted) is in a high-impedance state during the period (α) in FIG. 18. This will be explained in detail below.
During the period (α) in FIG. 18, the voltage of the input signal IN1 applied to the gate of the transistor 3 is at the low level. Therefore, the transistor 3 is OFF. Since the transistor 3 is OFF, the voltage of the output signal OUT1, being equal to the gate potential of the transistor 7, is also at the low level. Thus, the transistor 7 is also OFF. As a result, the portion between the source of the transistor 3 and the gate of the transistor 7 is in a high-impedance state.
If the portion between the source of the transistor 3 and the gate of the transistor 7 is in a high-impedance state as described above, the potential at this portion and the voltage of the output signal OUT1 will not stably stay at the low level during the period (α). This may result in, for example, the transistor 7, which should be turned OFF, being erroneously turned ON, thereby causing a malfunction of the shift register.